Field of the Invention
The present invention relates to a test configuration with an automatic test machine and an integrated circuit and to a method for determining the time behavior of an integrated circuit.
In integrated circuits, in particular in semiconductor memories, it is normally desirable to be able to detect the time behavior thereof exactly. In particular, the precise instant of data outputting or the time behavior of the data output window is of great interest in the case of high-speed memory chips. This is the case with single data rate (SDR) and with double data rate (DDR) synchronous dynamic random access memories (SDRAMs).
Normally, speed tests are carried out for high-performance memory chips during the manufacture thereof in order to determine the data output time window and, if appropriate, to segregate by sorting the memory modules which do not fulfil defined specifications.
During a read access, an SDRAM outputs data that are synchronized with respect to an external clock signal. In this case, the relative phase angle of the data signal output with respect to the predetermined clock signal lies in the range of a few nanoseconds or even in the range of picoseconds. The outlay for measuring whether or not a specific memory chip fulfils predetermined specifications, and the associated costs, increase ever further as the speed of the accesses increases and the data transfer rates rise.
The paper titled “Demodulation Based Testing of Off-Chip Driver Performance”, by W. Daehn, European Test Workshop, Informal Digest 2001, pages 93 to 98, specifies a method for testing the performance of the output drivers of integrated circuits. In this case, periodic signals are used which are analyzed in the frequency domain rather than in the time domain. Complicated analyses in the time domain can thus be simplified. However, in order to move from an analysis in the time domain to an analysis in the frequency domain, comparatively complicated signal processing is necessary. At the time of the patent application, this document was retrievable on the Internet for example under http://www.computer.org.digital library ETW01.
Published, Non-Prosecuted German Patent Application DE 100 45 671 A1 specifies a test apparatus and a test method for an integrated semiconductor circuit in which a circuit to be tested is driven by a test pattern generator. A measuring device is used to detect the waveform of the transient power supply current of the circuit to be tested. The waveform of the power supply current is evaluated by an error detector.